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1. general description the SC18IS600/601 is designed to serve as an interface between the standard spi of a host (microcontroller, microprocessor, chip set, etc.) and the serial i 2 c-bus. this allows the host to communicate directly with other i 2 c-bus devices. the SC18IS600/601 can operate as an i 2 c-bus master-transmitter or master-receiver. the SC18IS600/601 controls all the i 2 c-bus speci?c sequences, protocol, arbitration and timing. the key distinction between the SC18IS600 and the sc18is601 lies in the clock source: internal (SC18IS600) versus external (sc18is601). 2. features n spi slave interface n spi mode 3 n master i 2 c-bus controller n general purpose input/output (gpio) pins: 4 (SC18IS600); 3 (sc18is601) n two quasi-bidirectional i/o pins n 5 v tolerant i/o pins n high-speed spi: u up to 3 mbit/s (sc18is601) u up to 1.2 mbit/s (SC18IS600) n high-speed i 2 c-bus: 400 kbit/s n 96-byte transmit buffer n 96-byte receive buffer n 2.4 v to 3.6 v operation n power-down mode with w akeup pin n oscillator: internal (SC18IS600); external (sc18is601) n active low interrupt output n available in very small tssop16 package 3. ordering information SC18IS600/601 spi to i 2 c-bus interface rev. 03 13 december 2006 product data sheet table 1. ordering information type number package name description version SC18IS600ipw tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 sc18is601ipw
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 2 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 4. block diagram fig 1. block diagram of SC18IS600 SC18IS600 reset 002aab712 control logic interconnect bus lines and control signals mosi spi sclk cs miso interrupt control logic int oscillator buffer i 2 c-bus controller general purpose i/os gpio0 sda scl gpio1 gpio2 gpio3 io5 on-chip rc oscillator io4/wakeup
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 3 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface fig 2. block diagram of sc18is601 sc18is601 reset 002aab784 control logic interconnect bus lines and control signals mosi spi sclk cs miso interrupt control logic int oscillator general purpose i/os sda scl external clock input (clkin) buffer i 2 c-bus controller gpio0 gpio1 gpio2 io5 io4/wakeup
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 4 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 5. pinning information 5.1 pinning 5.2 pin description fig 3. SC18IS600 pin con?guration for tssop16 fig 4. sc18is601 pin con?guration for tssop16 SC18IS600ipw gpio0 io5 cs wakeup/io4 reset int v ss gpio3 miso v dd mosi sclk sda gpio2 scl gpio1 002aab713 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 sc18is601ipw gpio0 io5 cs wakeup/io4 reset int v ss clkin miso v dd mosi sclk sda gpio2 scl gpio1 002aab714 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin type description SC18IS600 sc18is601 gpio0 1 1 i/o programmable i/o pin cs 2 2 i chip select. when cs is low, the SC18IS600/601 is selected. reset 3 3 i master reset. when active (low), reset sets internal registers to the default values, and resets the i 2 c-bus and spi hardware. see t ab le 3 . v ss 4 4 i ground supply voltage miso 5 5 o spi slave data output mosi 6 6 i spi slave data input sda 7 7 i/o i 2 c-bus serial data input/output scl 8 8 o i 2 c-bus serial clock output gpio1 9 9 i/o programmable i/o pin gpio2 10 10 i/o programmable i/o pin sclk 11 11 i spi clock input v dd 12 12 i 2.4 v to 3.6 v supply voltage gpio3 13 - i/o programmable i/o pin clkin - 13 i external clock input int 14 14 o interrupt. when active (low), int informs the cpu that the SC18IS600/601 has an interrupt to be serviced. int is reset (deactivated) either when the i2cstat register is read or as a result of a master reset ( reset). this pin is an open-drain pin. w akeup/io4 15 15 i/o wake up the SC18IS600/601 from the power-down mode. pulled low by the host to wake-up from low power state. this pin can also be used as a quasi-bidirectional i/o when not in a power-down state. io5 16 16 i/o quasi-bidirectional i/o pin
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 5 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6. functional description the SC18IS600/601 acts as a bridge between a spi interface and an i 2 c-bus. it allows a spi master device to communicate with i 2 c-bus slave devices. the spi interface supports mode 3 of the spi speci?cation and can operate up to 3 mbit/s (sc18is601). 6.1 internal registers the SC18IS600/601 provides internal registers for monitoring and control. these registers are shown in t ab le 3 . register functions are more fully described in the following paragraphs. [1] for sc18is601, these bits are dont care. [2] for sc18is601 gpio3 is not used. 6.2 register descriptions 6.2.1 programmable io port con?guration register (iocon?g) pins gpio0 to gpio3 may be con?gured by software to one of four types. these are: quasi-bidirectional, push-pull, open-drain, and input-only. two con?guration bits per pin, located in the iocon?g register, select the io type for each pin. each pin has schmitt-triggered input that also has a glitch suppression circuit. io4 and io5 are quasi-bidirectional pins and are not user-con?gurable. for sc18is601, gpio3 is non-existent. t ab le 4 shows the con?gurations for the programmable i/o pins. iox.1 and iox.0 correspond to gpiox. table 3. internal registers summary register address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w default value 0x00 iocon?g io3.1 [1] io3.0 [1] io2.1 io2.0 io1.1 io1.0 io0.1 io0.0 r/w 0x00 0x01 iostate 0 0 gpio5 gpio4 gpio3 [2] gpio2 gpio1 gpio0 r/w 0x3f 0x02 i2cclock cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 r/w 0x19 0x03 i2cto to6 to5 to4 to3 to2 to1 to0 te r/w 0xfe 0x04 i2cstat 1 1 1 1 i2cstat3 i2cstat2 i2cstat1 i2cstat0 r 0xf0 0x05 i2cadr adr7 adr6 adr5 adr4 adr3 adr2 adr1 x r/w 0x00 table 4. pin con?gurations iox.1 iox.0 pin con?guration 0 0 quasi-bidirectional output con?guration 0 1 input-only con?guration 1 0 push-pull output con?guration 1 1 open-drain output con?guration
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 6 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.2.1.1 quasi-bidirectional output con?guration quasi-bidirectional outputs can be used both as an input and output without the need to recon?gure the pin. this is possible because when the pin outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a large current. there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. one of these pull-ups, called the very weak pull-up, is turned on whenever the pin latch for the pin contains a logic 1. this very weak pull-up sources a very small current that will pull the pin high if it is left ?oating. a second pull-up, called the weak pull-up, is turned on when the pin latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the pin below its input threshold voltage. the third pull-up is referred to as the strong pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional pin when the pin latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for two system clock cycles quickly pulling the pin high. the quasi-bidirectional pin con?guration is shown in figure 5 . although the SC18IS600/601 is a 3 v device, most of the pins are 5 v tolerant. if 5 v is applied to a pin con?gured in quasi-bidirectional mode, there will be a current ?owing from the pin to v dd causing extra power consumption. therefore, applying 5 v to pins con?gured in quasi-bidirectional mode is discouraged. a quasi-bidirectional pin has a schmitt-triggered input that also has a glitch suppression circuit. fig 5. quasi-bidirectional output con?guration 002aab882 2 system clock cycles weak strong very weak v dd ppp v ss pin latch data gpion, ion pin glitch rejection input data
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 7 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.2.1.2 open-drain output con?guration the open-drain output con?guration turns off all pull-ups and only drives the pull-down transistor of the pin when the pin latch contains a logic 0. to be used as a logic output, a pin con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . the pull-down for this mode is the same as for the quasi-bidirectional mode. the open-drain pin con?guration is shown in figure 6 . an open-drain pin has a schmitt-triggered input that also has a glitch suppression circuit. 6.2.1.3 input-only con?guration the input-only pin con?guration is shown in figure 7 . it is a schmitt-triggered input that also has a glitch suppression circuit. 6.2.1.4 push-pull output con?guration the push-pull output con?guration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the pin latch contains a logic 1. the push-pull mode may be used when more source current is needed from a pin output. the push-pull pin con?guration is shown in figure 8 . a push-pull pin has a schmitt-triggered input that also has a glitch suppression circuit. fig 6. open-drain output con?guration 002aab883 v ss pin latch data gpio pin glitch rejection input data fig 7. input-only con?guration 002aab884 gpio pin glitch rejection input data
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 8 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.2.2 i/o pins state register (iostate) when read, this register returns the actual state of all programmable and quasi-bidirectional i/o pins. when written, each register bit will be transferred to the corresponding i/o pin programmed as output. 6.2.3 i 2 c-bus address register (i2cadr) the contents of the register represents the devices own i 2 c-bus address. the most signi?cant bit corresponds to the ?rst bit received from the i 2 c-bus after a start condition. the least signi?cant bit is not used, but should be programmed with a 0. i2cadr is not needed for device operation, but should be con?gured so that its address does not con?ict with an i 2 c-bus device address used by the bus master. 6.2.4 i 2 c-bus clock rates register (i2cclk) this register determines the i 2 c-bus clock frequency. various clock rates are shown in t ab le 6 for the SC18IS600. the frequency can be determined using the following formula: fig 8. push-pull output con?guration 002aab885 strong v dd p v ss pin latch data gpio pin glitch rejection input data n table 5. iostate - i/o pins state register (address 0x01) bit description bit symbol description 7:6 - reserved 5 io5 set the logic level on the output pins. write to this register: logic 0 = set output pin to zero logic 1 = set output pin to one a read from this register returns states of all pins. 4 io4 3 gpio3 (SC18IS600 only) 2 gpio2 1 gpio1 0 gpio0 i 2 c - bus clock frequency 7.3728 10 6 4 i2cclk ------------------------------ - hz () =
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 9 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface the i 2 c-bus clock frequency for the sc18is601 can be determined using the following formula: 6.2.5 i 2 c-bus time-out register (i2cto) the time-out register is used to determine the maximum time that the i 2 c-bus master is allowed to complete a transfer before setting an i 2 c-bus time-out interrupt. the least signi?cant bit of i2cto (te bit) is used as a time-out enable/disable. a logic 1 will enable the time-out function. on the SC18IS600 the time-out oscillator operates at 57.6 khz. for the sc18is601 the time-out oscillator frequency can be determined using the following formula: this oscillator is fed into a 16-bit down counter. the down counters lower nine bits are loaded with 1, while the upper seven bits are loaded with the contents of i2cto. the time-out value is an approximate value. in the case of arbitration loss, the SC18IS600/601 will transmit a start condition when the bus becomes free unless the time-out condition is reached. if the time-out condition is reached, an interrupt will be generated on the int pin. the i 2 c-bus time-out status can be read in i2cstat. table 6. i 2 c-bus clock frequency example at 7.3728 mhz i2cclk (decimal) i 2 c-bus clock frequency 5 (minimum) 369 khz 7 263 khz 9 204 khz 19 97 khz 255 (maximum) 7.2 khz i 2 c - bus clock frequency clkin 4 i2cclk ---------------------------- hz () = table 7. i2cto - i 2 c-bus time-out register (address 0x04) bit description bit symbol description 7:1 to[7:1] time-out value 0 te enable/disable time-out function logic 0 = disable logic 1 = enable fig 9. time-out value time - out oscillator frequency clkin 128 ------------------ - hz () = 57.6 khz oscillator 002aab715 16-bit down counter [i2cto][111111111] time-out
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 10 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.2.6 i 2 c-bus status register (i2cstat) this register reports the results of i 2 c-bus transmit and receive transaction between SC18IS600/601 and an i 2 c-bus slave device. table 8. i 2 c-bus status register value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i 2 c-bus status description 0xf0 11110000tr ansmission successful. the SC18IS600/601 has successfully completed and i 2 c-bus read or write transaction. an interrupt is generated on int. this is also the default status after reset. no interrupt is generated after reset. 0xf1 11110001i 2 c-bus device address not acknowledged. no i 2 c-bus slave device has acknowledged the slave address that has been sent out in an i 2 c-bus read or write transaction. an interrupt is generated on int. 0xf2 11110010i 2 c-bus device address not acknowledged. an i 2 c-bus slave has not acknowledged the byte that has just been transmitted by the SC18IS600/601. an interrupt is generated on int. 0xf3 11110011i 2 c-bus busy. the SC18IS600/601 is busy performing an i 2 c-bus transaction, no new transaction should be initiated by the host. no interrupt is generated. 0xf8 11111000i 2 c-bus time-out (see section 6.2.5 i 2 c-b us time-out register (i2ct o) ). the SC18IS600/601 has started an i 2 c-bus transaction that has taken longer than the time programmed in i2cto register. this could happen after a period of unsuccessful arbitration or when an i 2 c-bus slave is (continuously) pulling the scl clock low. an interrupt is generated on int.) 0xf9 11111001i 2 c-bus invalid data count. the number of bytes speci?ed in a read or write command to the SC18IS600/601. an interrupt is generated on int.
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 11 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.3 external clock input (sc18is601) in this device, the processor clock is derived from an external source driving the clkin pin. the clock rate may be from 0 hz up to 18 mhz. 6.4 i 2 c-bus serial interface i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multi-master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus con?guration is shown in figure 10 . the SC18IS600/601 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. (refer to philips semiconductors the i 2 c-bus speci?cation , document order number 9398 393 40011.) 6.5 serial peripheral interface (spi) the host communicates with the SC18IS600/601 via the spi interface. the SC18IS600/601 operates in slave mode up to 3 mbit/s. the spi interface has four pins: sclk, mosi, miso, and cs. ? sclk , mosi and miso are typically tied together between two or more spi devices. data ?ows from the master to the SC18IS600/601 on the mosi (master out slave in) pin and ?ows from SC18IS600/601 to the master on the miso (master in slave out) pin. the sclk signal is an input to the SC18IS600/601. ? cs is the slave select pin. in a typical con?guration, an spi master selects one spi device as the current slave. an spi slave device uses its cs pin to determine whether it is selected. the cs pin may be tied low if it is the only device on the bus. typical connections are shown in figure 11 . fig 10. i 2 c-bus con?guration r pu 002aab716 v dd SC18IS600/601 i 2 c-bus device i 2 c-bus device i 2 c-bus sda scl r pu
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 12 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.6 spi message format 6.6.1 write n bytes to i 2 c-bus slave device the spi host issues the write command by sending a 0x00 command followed by the total number of bytes (maximum 96 bytes excluding the address) to send and an i 2 c-bus slave device address followed by i 2 c-bus data bytes, beginning with the ?rst byte (data byte 1) and ending with the last byte (data byte n). once the spi host issues this command, the SC18IS600/601 will access the i 2 c-bus slave device and start sending the i 2 c-bus data bytes. when the i 2 c-bus write transaction has successfully ?nished, and interrupt is generated on the int pin, and the transaction completed status can be read in i2cstat. note that the third byte sent by the host is the device i 2 c-bus slave address. the SC18IS600/601 will ignore the least signi?cant bit so a write will always be performed even if the least signi?cant bit is a 1. fig 11. spi single master multiple slaves con?guration 002aab717 master miso mosi spiclk port port slave sclk cs SC18IS600/601 slave sclk cs other spi device fig 12. write n bytes to i 2 c-bus slave device 002aab718 number of bytes 0x00 command slave address + w spi host sends data byte 1 data byte n cs sclk mosi data byte 1 data byte n 0 slave address a[7:1] number of bytes d[7:0] command 0x00
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 13 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.6.2 read n bytes from i 2 c-bus slave device once the host issues this command, the SC18IS600/601 will start an i 2 c-bus read transaction on the i 2 c-bus to the speci?ed slave address. once the data is received, the SC18IS600/601 will place this data in the receiver buffer, and will generate an interrupt on the int pin. the transaction completed status can be read in the i2cstat. note that the data is not returned until a read buffer command is performed (see section 6.6.4 read b uff er ). note that the third byte sent by the host is the device slave address. the SC18IS600/601 will ignore the least signi?cant bit so a read will always be performed even if the least signi?cant bit is a 0. the maximum number of bytes to be read is 96. 6.6.3 i 2 c-bus read after write once the host issues this command, the SC18IS600/601 will start a write transaction on the i 2 c-bus to the speci?ed slave address. once the data is written, the SC18IS600/601 will read data from the speci?ed slave, place the data in the receiver buffer and generate an interrupt on the int pin. the transaction completed status can be read in i2cstat. note that the data is not returned until a read buffer command is performed. 6.6.4 read buffer fig 13. read n bytes from i 2 c-bus slave device number of bytes 0x01 command slave address + r spi host sends cs sclk mosi 1 slave address a[7:1] number of bytes d[7:0] command 0x01 002aab719 fig 14. i 2 c-bus read after write 002aab720 number of write bytes 0x02 command slave address + w spi host sends data write byte 0 data write byte n number of read bytes slave address + r fig 15. read buffer 002aab868 0x06 command spi host sends data byte 1 data byte n
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 14 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface when the host issues a read buffer command, the SC18IS600/601 will return the data in the read buffer on the miso pin. note that the read buffer will be overwritten if an additional read n bytes or a read after write command is executed before the read buffer command. 6.6.5 i 2 c-bus write after write when the host issues this command, the SC18IS600/601 will ?rst write n data bytes to the i 2 c-bus slave 1 device followed by a write of m data bytes to the i 2 c-bus slave 2 device. 6.6.6 spi con?guration the spi con?guration command can be used to change the order in which the bits of spi data byte are sent on the spi bus. in the lsb ?rst con?guration (spi con?guration data is 0x42), bit 0 is the ?rst bit sent of any spi byte. in msb ?rst (spi con?guration data is 0x81), bit 7 is the ?rst bit sent. t ab le 9 shows the two possible con?gurations that can be programmed. fig 16. write after write 002aab721 number of bytes 1 0x03 command slave 1 address + w spi host sends data byte 1 data byte n number of bytes 2 slave 2 address + w data byte 1 data byte n fig 17. spi con?guration table 9. spi con?guration spi con?guration data order 0x42 lsb ?rst 0x81 msb ?rst (default) 002aab722 0x18 command spi configuration spi host sends cs sclk mosi spi configuration data character 0x18
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 15 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.6.7 write to SC18IS600/601 internal registers a write register function is initiated by sending a 0x20 command followed by an internal register address to be written (see section 6.1 ). the register data byte follows the register address. only one register can be accessed in a single transaction. there is no auto-incrementing of the register address. 6.6.8 read from SC18IS600/601 internal register a read register function is initiated by sending a 0x21 command followed by an internal register address to be read (see section 6.1 ) and a dummy byte. the data byte of the read register is returned by the SC18IS600 on the miso pin. only one register can be accessed in a single transaction. there is no auto-incrementing of the register address. note that write and read from internal registers are processed immediately as soon as the SC18IS600/601 determines the intended register. fig 18. write to SC18IS600/601 internal registers 002aab723 register x 0x20 command spi host sends data byte cs sclk mosi data byte register x character 0x20 fig 19. read from SC18IS600/601 internal register 0x21 command register data spi host sends cs sclk mosi dummy byte register x character 0x21 002aab724 miso data byte register x
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 16 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 6.6.9 power-down mode the SC18IS600/601 can be placed in a low-power mode where the internal oscillator is stopped and it will no longer respond to spi messages. enter the power-down mode by sending the power-down command (0x30) followed by the two de?ned bytes, which are 0x5a followed by 0xa5. if the exact message is not received, the device will not enter the power-down state. before entering the power-down state, w akeup/io4 should be placed in a high state. to exit the power-down state, the w akeup/io4 should be brought low. after leaving the power-down state, the w akeup/io4 can once again be used as a general-purpose io pin. 7. limiting values [1] this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated max imum. [2] parameters are valid over the operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [3] based on package heat transfer, not device power consumption. fig 20. power-down mode 002aab725 0x30 command spi host sends 0x5a cs sclk mosi character 0xa5 character 0x5a character 0x30 0xa5 table 10. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] [2] symbol parameter conditions min max unit t amb(bias) bias ambient temperature operating - 55 +125 c t stg storage temperature - 65 +150 c v n voltage on any other pin referenced to v ss - 0.5 +5.5 v i oh(i/o) high-state output current per input/output pin - 8 ma i ol(i/o) low-state output current per input/output pin - 20 ma i i/o(tot)(max) maximum total i/o current - 120 ma p tot /pack total power dissipation per package [3] - 1.5 w
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 17 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 8. static characteristics [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. [2] pin capacitance is characterized but not tested. [3] measured with pins in quasi-bidirectional mode. [4] measured with pins in high-impedance mode. [5] pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups). [6] pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. this cur rent is highest when v i is approximately 2 v. table 11. static characteristics v dd = 2.4 v to 3.6 v; t amb = - 40 cto+85 c (industrial); unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd(oper) operating supply current v dd = 3.6 v; f = 12 mhz - 7 13 ma v dd = 3.6 v; f = 18 mhz - 11 16 ma i dd(idle) idle mode supply current v dd = 3.6 v; f = 12 mhz - 3.6 4.8 ma v dd = 3.6 v; f = 18 mhz - 4 6 ma i dd(tpd) total power-down mode supply current v dd = 3.6 v; industrial - < 0.1 5 m a v dd = 3.6 v; extended - - 50 m a v th(hl) high-low threshold voltage schmitt trigger input 0.22v dd 0.4v dd -v v th(lh) low-high threshold voltage schmitt trigger input - 0.6v dd 0.7v dd v v hys hysteresis voltage - 0.2v dd -v v ol low-level output voltage all pins; i ol = 20 ma - 0.6 1.0 v all pins; i ol = 10 ma - 0.3 0.5 v all pins; i ol = 3.2 ma - 0.2 0.3 v v oh high-level output voltage all pins; i oh = - 8 ma; push-pull mode v dd - 1- - v all pins; i oh = - 3.2 ma; push-pull mode v dd - 0.7 v dd - 0.4 - v all pins; i oh = - 20 m a; quasi-bidirectional mode v dd - 0.3 v dd - 0.2 - v c ig input capacitance at gate [2] - - 15 pf i il low-level input current logical 0; v i = 0.4 v [3] -- - 80 m a i li input leakage current all ports; v i =v il or v ih [4] -- 10 m a i thl high-low transition current all ports; logical 1-to-0; v i = 2.0 v at v dd = 3.6 v [5] [6] - 30 - - 450 m a r reset_n(int) internal pull-up resistance on pin reset 10 - 30 k w
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 18 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 9. dynamic characteristics [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. [2] scl and sda do not have glitch suppression circuits. table 12. dynamic characteristics v dd = 2.4 v to 3.6 v; t amb = - 40 cto+85 c (industrial); unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max f osc(rc) internal rc oscillator frequency (SC18IS600) nominal f = 7.3728 mhz; trimmed to 1 % at t amb =25 c 7.189 7.557 7.189 7.557 mhz external clock input (sc18is601); see figure 22 f osc oscillator frequency v dd = 2.4 v to 3.6 v 0 12 - - mhz t clcl clock cycle time 83 - - - ns t chcx clock high time 22 t clcl - t clcx 22 - ns t clcx clock low time 22 t clcl - t chcx 22 - ns t clch clock rise time - 8 - 8 ns t chcl clock fall time - 8 - 8 ns glitch ?lter t gr [2] glitch rejection time reset pin - 50 - 50 ns any pin except reset - 15 - 15 ns t sa signal acceptance time reset pin 125 - 125 - ns any pin except reset 50 - 50 - ns spi slave interface f spi spi operating frequency 2.0 mhz 0 fosc 6 0 2.0 mhz t spicyc spi cycle time 2.0 mhz 6 fosc - 500 - ns t spilead spi enable lead time 2.0 mhz 4 - 4 - m s t spilag spi enable lag time 4 - 4 - m s t spiclkh spiclk high time 3 fosc - 190 - ns t spiclkl spiclk low time 3 fosc - 190 - ns t spidsu spi data setup time 100 - 100 - ns t spidh spi data hold time 100 - 100 - ns t spia spi access time 0 120 0 120 ns t spidis spi disable time 2.0 mhz 0 240 - 240 ns t spidv spi enable to output data valid time 2.0 mhz 0 240 - 240 ns 3.0 mhz 0 167 - 167 ns t spioh spi output data hold time 0-0-ns t spir spi rise time spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif spi fall time spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 19 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. [2] scl and sda do not have glitch suppression circuits. table 13. dynamic characteristics v dd = 3.0 v to 3.6 v; t amb = - 40 cto+85 c (industrial); unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =18mhz unit min max min max f osc(rc) internal rc oscillator frequency (SC18IS600) nominal f = 7.3728 mhz; trimmed to 1 % at t amb =25 c 7.189 7.557 7.189 7.557 mhz external clock input (sc18is601); see figure 22 f osc oscillator frequency 0 18 - - mhz t clcl clock cycle time 55 - - - ns t chcx clock high time 22 t clcl - t clcx 22 - ns t clcx clock low time 22 t clcl - t chcx 22 - ns t clch clock rise time - 5 - 5 ns t chcl clock fall time - 5 - 5 ns glitch ?lter t gr [2] glitch rejection time reset pin - 50 - 50 ns any pin except reset - 15 - 15 ns t sa signal acceptance time reset pin 125 - 125 - ns any pin except reset 50 - 50 - ns spi slave interface f spi spi operating frequency 3.0 mhz 0 fosc 6 0 3 mhz t spicyc spi cycle time 3.0 mhz 6 fosc - 333 - ns t spilead spi enable lead time 3.0 mhz 4 - 4 - m s t spilag spi enable lag time 3.0 mhz 4 - 4 - m s t spiclkh spiclk high time 3 fosc - 167 - ns t spiclkl spiclk low time 3 fosc - 167 - ns t spidsu spi data setup time 100 - 100 - ns t spidh spi data hold time 100 - 100 - ns t spia spi access time 0 80 0 80 ns t spidis spi disable time 3.0 mhz 0 160 - 160 ns t spidv spi enable to output data valid time 3.0 mhz 0 160 - 160 ns t spioh spi output data hold time 0 - 0 - ns t spir spi rise time spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif spi fall time spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 20 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface fig 21. spi slave timing (mode 3) t clcl t spiclkl t spiclkh t spilead t spilag t spidsu t spidh t spidh t spidsu t spif t spia t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spif ss 002aab797 spiclk (input) miso (output) mosi (input) t spidsu t spir t spir t spioh t spidv t spioh t spidv fig 22. external clock timing t chcl t clcx t chcx t clcl t clch 002aab886 0.2v dd + 0.9 v 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 21 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface table 14. additional spi ac characteristics symbol parameter conditions min typ max unit t spiclkw spiclk high time between two spi bytes 8 - - m s t csw cs high time between two spi transactions refer to figure 24 m s t spilag1 spi enable lag time 1 in a spi to i 2 c-bus transaction refer to figure 25 m s t d delay time from last sclk pulse to sda low in a spi to i 2 c-bus transaction refer to figure 26 m s fig 23. spi to i 2 c-bus timing diagram 002aab927 cs sclk sda t spilead t spiclkw t spilag1 t csw t d fig 24. t csw as a function of clkin frequency fig 25. t spilag1 as a function of clkin frequency fig 26. t d as a function of clkin frequency 8 t csw ( m s) 0 clkin frequency (mhz) 002aab929 1.843 18.00 7.373 12.00 3.687 6 4 2 5 t spilag1 ( m s) 0 clkin frequency (mhz) 002aab930 1.843 18.00 7.373 12.00 3.687 1 2 3 4 160 t d ( m s) 0 clkin frequency (mhz) 002aab931 1.843 18.00 7.373 12.00 3.687 80 40 120
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 22 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 10. package outline fig 27. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 23 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 11. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 11.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 11.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 11.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 24 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 11.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 28 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 15 and 16 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 28 . table 15. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 16. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 25 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 12. abbreviations msl: moisture sensitivity level fig 28. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 17. abbreviations acronym description ascii american standard code for information interchange gpio general purpose input/output uart universal asynchronous receiver/transmitter lsb least signi?cant bit msb most signi?cant bit i 2 c-bus inter ic bus spi serial peripheral interface
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 26 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 13. revision history table 18. revision history document id release date data sheet status change notice supersedes SC18IS600_601_3 20061213 product data sheet - SC18IS600_601_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? figure 1 bloc k diag r am of SC18IS600 and figure 2 bloc k diag r am of sc18is601 modi?ed: removed (input) directional arrow for signal scl ? t ab le 2 pin descr iption , signal scl: changed type from i/o to o; changed description from i 2 c-bus serial clock input/output to i 2 c-bus serial clock output ? t ab le 8 i 2 c-b us status : added column register value ? section 6.6.8 read from SC18IS600/601 inter nal register : C figure 19 read from SC18IS600/601 inter nal register modi?ed: changed register data to dummy byte on signal mosi C 1 st paragraph, 1 st sentence: appended and a dummy byte to end of sentence ? t ab le 14 additional spi a c char acter istics : t spiclkw minimum value changed from 3 m s to 8 m s SC18IS600_601_2 20060811 product data sheet - SC18IS600_601_1 SC18IS600_601_1 20060224 product data sheet - -
SC18IS600_601_3 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 03 13 december 2006 27 of 28 nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 14.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 14.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 15. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors SC18IS600/601 spi to i 2 c-bus interface ? nxp b.v. 2006. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 13 december 2006 document identifier: SC18IS600_601_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 internal registers. . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 register descriptions . . . . . . . . . . . . . . . . . . . . 5 6.2.1 programmable io port con?guration register (iocon?g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1.1 quasi-bidirectional output con?guration . . . . . . 6 6.2.1.2 open-drain output con?guration . . . . . . . . . . . . 7 6.2.1.3 input-only con?guration . . . . . . . . . . . . . . . . . . 7 6.2.1.4 push-pull output con?guration . . . . . . . . . . . . . 7 6.2.2 i/o pins state register (iostate) . . . . . . . . . . . . 8 6.2.3 i 2 c-bus address register (i2cadr) . . . . . . . . . . 8 6.2.4 i 2 c-bus clock rates register (i2cclk) . . . . . . . . 8 6.2.5 i 2 c-bus time-out register (i2cto) . . . . . . . . . . . 9 6.2.6 i 2 c-bus status register (i2cstat). . . . . . . . . . . 10 6.3 external clock input (sc18is601). . . . . . . . . . 11 6.4 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . 11 6.5 serial peripheral interface (spi) . . . . . . . . . . . 11 6.6 spi message format . . . . . . . . . . . . . . . . . . . . 12 6.6.1 write n bytes to i 2 c-bus slave device. . . . . . . 12 6.6.2 read n bytes from i 2 c-bus slave device . . . . 13 6.6.3 i 2 c-bus read after write. . . . . . . . . . . . . . . . . . 13 6.6.4 read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.6.5 i 2 c-bus write after write . . . . . . . . . . . . . . . . . 14 6.6.6 spi con?guration . . . . . . . . . . . . . . . . . . . . . . 14 6.6.7 write to SC18IS600/601 internal registers . . . 15 6.6.8 read from SC18IS600/601 internal register. . 15 6.6.9 power-down mode . . . . . . . . . . . . . . . . . . . . . 16 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 8 static characteristics. . . . . . . . . . . . . . . . . . . . 17 9 dynamic characteristics . . . . . . . . . . . . . . . . . 18 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 11 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.1 introduction to soldering . . . . . . . . . . . . . . . . . 23 11.2 wave and re?ow soldering . . . . . . . . . . . . . . . 23 11.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 11.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 14 legal information . . . . . . . . . . . . . . . . . . . . . . 27 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 14.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15 contact information . . . . . . . . . . . . . . . . . . . . 27 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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